Evaluation of the degradation of floating-gate memories with Al2O3 tunnel oxide

被引：0

作者：

Buckley, J. ^{[1
]}

Molas, G. ^{[1
]}

Gely, M. ^{[1
]}

Martin, F. ^{[1
]}

Pananakakis, G. ^{[3
]}

Bongiorno, C. ^{[2
]}

Lombardo, S. ^{[2
]}

机构：

[1] CEA, LETI, 17 Rue Martys, F-38054 Grenoble 9, France

[2] CNR, IMM, I-95121 Catania, Italy

[3] IMEP CNRS, F-38016 Grenoble, France

来源：

ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Replacing the tunnel oxide of non-volatile memories by a high-k dielectric is addressed in this paper. This work reports in its first part an experimental study of conduction and trapping in Al2O3 layers. The experimental data of these layers is then integrated in a novel endurance model suitable for flash memories with high-k tunnel oxide. Simulation results show that low (+8/-7V) operating voltages can be used to obtain large threshold voltage shifts, and despite a great amount of trapped negative charges (several 10(12)/CM,), the programming window isn't closed after 10(7) write/erase (W/E) cycles.

引用

页码：246 / +

页数：2

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