A 1.8V 200mW 8-bit 1GSPS CMOS A/D Converter with a Cascaded-Folding and an Interpolation

被引：0

作者：

Hwang, Jooho ^{[1
]}

Lee, Dongheon ^{[1
]}

Park, Sunghyun ^{[1
]}

Moon, Junho ^{[1
]}

Song, Minkyu ^{[1
]}

机构：

[1] Dongguk Univ, Dept Semicond Sci, Seoul 100715, South Korea

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2009年

关键词：

ADC; cascaded-folding; folder averaging; auto-switching encoder;

D O I：

10.1109/ICICDT.2009.5166304

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 mu m 1-poly 5-metal CMOS technology. The active chip area is 0.72mm(2) and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when F(in)= F(s)/2 at F(s)=1GHz.

引用

页码：241 / 244

页数：4

共 35 条

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