Analog and Short Channel Effects Performance of Sub-100 nm Graded Channel Fully Depleted Silicon On Insulator (SOI)

被引：0

作者：

Jafar, Norsyahida ^{[1
]}

Soin, Norhayati ^{[1
]}

机构：

[1] Univ Malaya, Fac Engn, Dept Elect, Kuala Lumpur, Malaysia

来源：

MINO'09: PROCEEDINGS OF THE 8TH WSEAS INTERNATIONAL CONFERENCE ON MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS: ADVANCES IN MICROELECTRONICS, NANOELECTRONICS AND OPTOELECTRONICS | 2009年

关键词：

Graded Channel Fully Depleted SOI; SOI; analog; Short Channel Effects (SCEs); GATE; MODEL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the dependency of analog and Short Channel Effects (SCEs) performance of 75 nm channel length fully-depleted Silicon On Insulator (SOI) device on the applied Graded Channel (GC) design. The comparative analysis between standard SOI (STD SOI) devices at doped channel and equivalent threshold voltage, V-TH with GC SOI device are examined on the basis of internal physical mechanisms. Device characterizations are performed using simulation based approached provided by ATLAS 2D. Results show superiority of GC performances over standard SOI devices in both analog and SCEs point of views.

引用

页码：63 / 67

页数：5

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