Highly Parallel Writing Strategy Based on Diagonal-Gates-Connection 1T1R Arrays

Large-scale memristor arrays with multivalued characteristics bring the gospel to applications such as non-volatile memory and neuromorphic computing. The memristor-accurate modulation often requires multiple SET and RESET operations. Nonetheless, the most mature one-MOSFET-one-memristor (1T1R) array cannot support SET and RESET operation at different devices parallelly, which limits the array writing speed. In this work, we build a diagonal-gates-connection (DGC) memristor array model based on the practical TiN/HfOx/TaOx/TiN 1T1R device. Within the DGC array, devices sharing the common slope word line (SWL) can be SET or RESET independently at the same time for each device having an independent bitline (BL) and source line (SL). Furthermore, a sliding-window acquisition (SWA) strategy is proposed to optimize the writing performance of the DGC 1T1R array. In the simulation of digital image storage, the writing efficiency of DGC array has been significantly improved by utilizing the new SWA strategy, which achieves two data level improvements compared to traditional 1T1R arrays. This work demonstrates that large-scale memristor arrays operating in parallel hold great promise for applications that rely on high writing speed.