A new ultra-thin 3D integration technique: Technological and thermal investigations

被引：0

作者：

Pinel, S ^{[1
]}

Tasselli, J ^{[1
]}

Marty, A ^{[1
]}

Bailbe, JP ^{[1
]}

Beyne, E ^{[1
]}

Van Hoof, R ^{[1
]}

Marco, S ^{[1
]}

Leseduarte, S ^{[1
]}

Vendier, O ^{[1
]}

Vera, AC ^{[1
]}

机构：

[1] CNRS, LAAS, F-31077 Toulouse 4, France

来源：

DESIGN, TEST, INTEGRATION, AND PACKAGING OF MEMS/MOEMS, PROCEEDINGS | 2000年 / 4019卷

关键词：

3D integration; ultra-thin chips; thermal simulations;

D O I：

10.1117/12.382262

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A new vertical chip integration is proposed, based on the UTCS (Ultra Thin Chip Stack(1)) concept. It consists in stacking thinned chips (near 10 mu m) on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This Wafer Scale Integration technique is presented. Thermal behavior of such stacked structure is also discussed.

引用

页码：324 / 332

页数：9

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