A study on interface layer with annealing conditions of ZrO2/ZrSixOy high-k gate oxide

Aggressive scaling-down has led to thermal-dioxide (SiO2) gate dielectrics as thin as 2.0 - 2.5 nm in MOS (Metal-Oxide-Semiconductor) technologies. As a consequence, leakage current due to direct tunneling through the gate oxide has been increasing exponentially. Recently, a variety of alternative high-k materials (e.g. HfO2, ZrO2, and their silicate) have been reported as feasible replacements for thermal dioxide (SiO2) to Solve the gate leakage current and limit-of-scaling problems. In this work, we focus on clarifying the role of annealing conditions influencing the ZrO2/ZrSixOy, characteristics. ZrO2/ZrSixOy high-k gate oxides were simply formed by oxidizing Zr film (60 angstrom) deposited on Si substrate at 500 degrees C for 2 hr under O-2 ambient. Annealing was done at 500 degrees C for 1 hr by using various ambient gases (i.e., N-2, N2O, and O-2). A conventional furnace was used for both oxidation and annealing. Using the physical-characterization tools (AFM, XPS, etc.) and the electrical measurement techniques (C-V, I-V, FNT. etc.) we confirmed that oxidation of thin Zr films on Si results in a ZrO2/ZrSixOy stack layer with excellent properties, that is, negligible hysteresis, excellent EOT value, and low leakage current. No significant differences in density of interface traps (D-it) and EOT were observed as a function of annealing gas; the rates of Dit and EOT were 9.56 x 10(11) similar to 1.26 x 10(12) eV(-1) cm(-2) and 22.7 similar to 26.6, respectively. However, the ranges of V-fb and leakage current values change depending on the annealing gases; these were -0.3 similar to 0.18 V and 1.61 x 10(-7) similar to 9.8 x 10(-3) A/cm(2) at -1 V, respectively. In general, the best electrical properties were obtained from the samples subjected to O-2 annealing.