Impact of array data flow analysis on the design of energy-efficient circuits

dThe grade of abstraction (specification level) for designing digital circuits has risen in the recent years from RT over algorithmic up to system level. An ambitious challenge of the EDA is to provide an efficient design space exploration with design-solutions comparable to hand-crafted optimisations. The accuracy of the legal design space directly influences the efficiency of automatically generable designs. Current Design-Tools do not exploit the freedom that is enabled by array data-flow analysis (ADFA). This paper shows the impact of our ADFA on behavioural synthesis and estimation for the metrics execution-time, area, and energy. Data-flow intensive benchmarks show improvements of up to 12% less energy and 30% less execution-time while area varies by +/- 15%.