Novel strategy for wafer induced shift (WIS)

Alignment error that originates in the actual wafer process is one of the factors that deteriorates total overlay accuracy. This error is known as wafer induced shift (WIS). WIS occurs through a change of alignment mark topography during the actual wafer processing. To reduce this error, we propose a tool that will simulate an alignment offset generated by WIS. We have called this tool the Alignment Offset Analyzer. The Alignment Offset Analyzer consists of a profiler for measuring the alignment mark topography and a simulator that simulates the alignment offset. By using the Alignment Offset Analyzer, we simulate the alignment signals from a Tungsten chemical mechanical polishing (CMP) wafer. The simulated alignment signals have an asymmetric shape due to the wafer processing. With these signals, the alignment offset caused by WIS can be estimated prior to the exposure sequence.