Design of an Efficient Adder based on Residue Number System

In this paper, a new modified approach is implemented with gates which consists of OR, AND gales and RNS based ALU (Arithmetic and Logical Unit) is implemented The technology used is Xilinx ISE 14.7 Verilog coding for these adders The conventional structure consists of imix's where convening from one form to another form is required The two technique named, thermometer and one-hot coding are very usefuL The disadvantages with the conventional approach are area, power and delay. In VLSI, the major factors are speed, are and delay This paper attempts to reduce the power and maintain efficiency The proposed research work is . further extended to increase the bit size and design modular adder with various moduli i.e, extended the feature of coding which works for mod 5, 7, 11, and 13. In this, paper to understand the methodology modulo-7, modulo-8 based modular adders are designed with logic gates and a modified architecture is presented and a basic comparison is shown between binary and residue number system The parameters of both the techniques are compared and the proposed methods shows best results compare to traditional methods.