Design of One-Transistor SRAM Cell for Low Power Consumption

In this work one-transistor static random access memory cell (SRAM) to reduce power consumption using tunnel diode as basic latching circuit element is designed and simulated. The SRAM cell consists of a transistor (nMOSFET) having effective gate length of 18nm and a pair of Si-Ge Tunnel diode having current peak to valley current ratio (PVR) of value 1.67 each. The bistability of the back-to-back series connected tunnel diode pair is used to hold the states of the designed SRAM cell and the pass transistor is used to control the switching of the tunnel diode. The changing in the state of the designed SRAM is observed by the variation of drain current (ID) of the transistor. This SRAM cell highly reduces the power dissipation compared to conventional SRAM cell and other SRAM cell structures.