An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

The main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost-effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.