Streamline verification process with formal property verification to meet highly compressed design cycle

被引：0
|
作者：
Chatterjee, P [1 ]
机构：
[1] NVIDIA Corp, Santa Clara, CA 95056 USA
来源：
42nd Design Automation Conference, Proceedings 2005 | 2005年
关键词：
formal verification;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, I describe a methodology and tool flow for using formal verification effectively to reduce the verification burden in large custom ASIC designs.
引用
收藏
页码：674 / 677
页数：4
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