Stable high-order delta-sigma DACs

被引：0

作者：

Kiss, P ^{[1
]}

Arias, J ^{[1
]}

Li, DD ^{[1
]}

机构：

[1] Agere Syst, Dept Commun Circuits Res, Berkeley Hts, NJ 07922 USA

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Stability analysis of high-order delta-sigma loops is a challenge. In this work, a novel design criterion is presented for high-order multibit error-feedback DACs which are especially suitable for high-speed operation. This criterion allows the design of stable, robust, and high-resolution delta-sigma DACs. Both analytical and numerical analysis are performed for verification.

引用

页码：985 / 988

页数：4

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