Low-power content addressable memory (CAM) array for mobile devices

Large-capacity content-addressable memory (CAM) is beneficial in a variety of applications that require highspeed lookup table. It is used extensively in low power CPU design, network routers, and cache controllers. Content addressable memory system includes CAM cells that contains a compare-circuit and a memory bit-cell that stores complementary bits. The compare circuit consists of complementary inputs to receive the complementary stored bits, and an input node to receive a single-ended reference bit. The main CAM design challenge is to reduce the power consumption associated with large amount of parallel switching circuitry, without sacrificing speed or density. This paper presents a novel CAM circuit level implementation aiming at reducing the comparator power and the crowbar current. Consequently, the average current consumption during CAM operation is reduced. In addition, the proposed circuit topology eliminates the need to route the complementary data which saves routing resources. Simulation results using 22 nm process technology shows that the elimination of the crowbar current during writing operation saves 40% of power for single bit-cell CAM, while sharing the compare circuitry among 8 bit-cells CAM saves 14% of the power without any performance impact regarding chip area.