A high performance 1.5V, 0.10μm gate length CMOS technology with scaled copper metallization

被引：13

作者：

Gilbert, P ^{[1
]}

Yang, I ^{[1
]}

Pettinato, C ^{[1
]}

Angyal, M ^{[1
]}

Boeck, B ^{[1
]}

Fu, C ^{[1
]}

VanGompel, T ^{[1
]}

Tiwari, R ^{[1
]}

Sparks, T ^{[1
]}

Clark, W ^{[1
]}

Dang, C ^{[1
]}

Mendonca, J ^{[1
]}

Chu, B ^{[1
]}

Lucas, K ^{[1
]}

Kling, M ^{[1
]}

Roman, B ^{[1
]}

Park, E ^{[1
]}

Huang, F ^{[1
]}

Woods, M ^{[1
]}

Rose, D ^{[1
]}

McGuffin, K ^{[1
]}

Nghiem, A ^{[1
]}

Banks, E ^{[1
]}

McNelly, T ^{[1
]}

Feng, C ^{[1
]}

Sturtevant, J ^{[1
]}

De, H ^{[1
]}

Das, A ^{[1
]}

Veeraraghavan, S ^{[1
]}

Nkansah, F ^{[1
]}

Bhat, M ^{[1
]}

机构：

[1] Motorola Inc, Networking & Comp Syst Grp, Austin, TX 78721 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746526

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high performance 0.10 mu m gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10 mu m-0.13 mu m gate length with physical 3 nm gate oxides and 0.175 mu m local interconnect features are optimized for 1.5V operation to achieve a 15 ps unloaded ring oscillator delay. Complementary Phase Shift Masks (c:PSM) for superior gate control and Low-K dielectrics for reduced coupling capacitance enable an aggressive (>15%) linear shrink of the previous generation copper-based technology [1]. Critical technology layer pitches summarized in Table 1 enable fabrication of 4.5 mu m(2) 6T-SRAM cells.

引用

页码：1013 / 1016

页数：4

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