Neural network implementation on a FPGA

被引：0
|
作者：
Chen, YJ [1 ]
du Plessis, WP [1 ]
机构：
[1] Univ Pretoria, ZA-0002 Pretoria, South Africa
来源：
2002 IEEE AFRICON, VOLS 1 AND 2: ELECTROTECHNOLOGICAL SERVICES FOR AFRICA | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This work implemented a feed forward neural network on a FPGA (field programmable gate array). A study was conducted to find the minimum precision required to maintain a recognition rate of at least 95% for two characters within an optical character recognition application. To reduce the circuit size, the bit serial architecture was realised to perform the arithmetic operation. This resulted in an optimal use of the FPGA resources.
引用
收藏
页码：337 / 342
页数：6
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