共 50 条
- [1] Test Cost Optimization Technique for the Pre-Bond Test of 3D ICs [J]. 2012 IEEE 30TH VLSI TEST SYMPOSIUM (VTS), 2012, : 102 - 107
- [2] Pre-Bond Probing of TSVs in 3D Stacked ICs [J]. 2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2011,
- [3] Vernier ring based pre-bond through silicon vias test in 3D ICs [J]. IEICE ELECTRONICS EXPRESS, 2017, 14 (18):
- [4] Identification of Defective TSVs in Pre-Bond Testing of 3D ICs [J]. 2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 187 - 194
- [5] Synthesis of 3D Clock Tree with Pre-bond Testability [J]. 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 2654 - 2657
- [6] Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores [J]. 2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2011, : 90 - 95
- [7] An Optimal Probing Method of Pre-Bond TSV Fault Identification in 3D Stacked ICs [J]. 2014 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2014,
- [8] Faulty TSVs Identification and Recovery in 3D Stacked ICs During Pre-bond Testing [J]. 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
- [10] A Cost-Effective pre-Bond Functional Test Architecture for 3D SoCs [J]. PROCEEDINGS OF 2016 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM), 2016, : 242 - 247