Configuration and debug of field programmable gate arrays using MATLAB®/SIMULINK®

Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB (R) model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB (R) model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK (R) model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use.