A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC

被引：0

作者：

Kuramochi, Yasuhide ^{[1
]}

Kawabata, Masayuki ^{[1
]}

Uekusa, Kouichiro ^{[1
]}

Matsuzawa, Akira ^{[2
]}

机构：

[1] Advantest Corp, Gunma R&D Ctr, Gunma 3700718, Japan

[2] Tokyo Inst Technol, Tokyo 1528552, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 11期

关键词：

analog to digital converter; charge redistribution type digital to analog converter; successive approximation architecture; calibration technique;

D O I：

10.1587/transele.E93.C.1630

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-mu m CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

引用

页码：1630 / 1637

页数：8

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