A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC

被引：0

作者：

Kuramochi, Yasuhide ^{[1
]}

Kawabata, Masayuki ^{[1
]}

Uekusa, Kouichiro ^{[1
]}

Matsuzawa, Akira ^{[2
]}

机构：

[1] Advantest Corp, Gunma R&D Ctr, Gunma 3700718, Japan

[2] Tokyo Inst Technol, Tokyo 1528552, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 11期

关键词：

analog to digital converter; charge redistribution type digital to analog converter; successive approximation architecture; calibration technique;

D O I：

10.1587/transele.E93.C.1630

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-mu m CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

引用

页码：1630 / 1637

页数：8

共 50 条

[21] A self-calibration technique for time-interleaved pipeline ADCs
Hakkarainen, V
Sumanen, L
Aho, M
Waltari, M
Halonen, K
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING, 2003, : 825 - 828
[22] A digital background calibration technique for SAR ADC based on capacitor swapping
Du, Ling
Ning, Ning
Wu, Shuangyi
Yu, Qi
Liu, Yang
IEICE ELECTRONICS EXPRESS, 2014, 11 (12):
[23] A 12-bit 32MS/s SAR ADC Using Built-in Self Calibration Technique To Minimize Capacitor Mismatch
Jung, In-Seok
Kim, Yong-Bin
PROCEEDINGS OF THE 2014 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS), 2014, : 276 - 280
[24] A 12-bit Fully Differential SAR ADC with a Novel Capacitor Mismatch Calibration
Peng, Xizhu
Liu, Hanpeng
Liu, Yuke
Tang, He
2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM), 2021,
[25] Background capacitor mismatch calibration for pipelined ADC
El-Sankary, K
Sawan, M
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 164 - 167
[26] Calibration of mismatch errors in time interleaved ADCs
Rudberg, MK
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 845 - 848
[27] Calibration for Split Capacitor DAC in SAR ADC
Li, Zhe
Lu, Yuxiao
Mo, Tingting
2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
[28] Mismatch and Offset Calibration in Redundant SAR ADC
Lopez-Angulo, Antonio
Gines, Antonio
Peralias, Eduardo
Rueda, Adoracion
2019 XXXIV CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), 2019,
[29] LMS-based digital background mismatch calibration technique for SAR ADC
Wan, Jing
Song, Shida
Liang, Yuhua
MICROELECTRONICS JOURNAL, 2023, 136
[30] Modeling of channel mismatch in time-interleaved SAR ADC
Li Dengquan
Zhang Liang
Zhu Zhangming
Yang Yintang
JOURNAL OF SEMICONDUCTORS, 2015, 36 (09)

← 1 2 3 4 5 →