Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers

The settling performance design of operational amplifiers is an important issue in discrete-time system applications. Most of the currently existing approaches achieve settling time-oriented design based on an approximate analytical transfer function model, and the result is inaccurate. A method for the exact settling performance-driven design of three-stage nested-Miller-compensated CMOS amplifiers is proposed in this paper. With the user-specified settling time at a certain accuracy level, this method finds the optimal solution by a two-step strategy, where the parameters of the compensation network are first solved from the equations formulated based on the minimal settling condition, and then the transconductance of the last stage is adjusted automatically according to the targeted settling time. The accuracy of the method is guaranteed by the use of the SPICE simulation of the settling waveform in the entire procedure. When the process variations are considered, an accurate worst-case design method is further developed. The method also features high efficiency compared with conventional optimization-based approaches. Experimental results of the simulated design in a 90 nm technology are provided to validate the effectiveness of the method.