Design of routing-constrained low power scan chains

被引:37
|
作者
Bonhomme, Y [1 ]
Girard, P [1 ]
Guiller, L [1 ]
Landrault, C [1 ]
Pravossoudovitch, S [1 ]
Virazel, A [1 ]
机构
[1] Univ Montpellier 2, CNRS, Lab Informat Robot & Microelect Montpellier, F-34392 Montpellier 5, France
关键词
D O I
10.1109/DATE.2004.1268828
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Scan-based architectures, though widely used in modem designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains [1]. The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.
引用
收藏
页码:62 / 67
页数:6
相关论文
共 50 条
  • [1] Design of routing-constrained low power scan chains
    Bonhomme, Y
    Girard, P
    Guiller, L
    Landrault, C
    Pravossoudovitch, S
    Virazel, A
    [J]. DELTA 2004: SECOND IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST APPLICATIONS, PROCEEDINGS, 2004, : 287 - 292
  • [2] Power-driven routing-constrained scan chain design
    Bonhomme, Y
    Girard, P
    Guiller, L
    Landrault, C
    Pravossoudovitch, S
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2004, 20 (06): : 647 - 660
  • [3] Power-Driven Routing-Constrained Scan Chain Design
    Y. Bonhomme
    P. Girard
    L. Guiller
    C. Landrault
    S. Pravossoudovitch
    [J]. Journal of Electronic Testing, 2004, 20 : 647 - 660
  • [4] Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing
    Girard, Patrick
    Bonhomme, Yannick
    [J]. JOURNAL OF LOW POWER ELECTRONICS, 2005, 1 (01) : 85 - 95
  • [5] Wrapper scan chains design for rapid and low power testing of embedded cores
    Han, YH
    Hu, Y
    Li, XW
    Li, HW
    Chandra, A
    Wen, XQ
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2005, E88D (09): : 2126 - 2134
  • [6] On optimizing scan testing power and routing cost in scan chain design
    Hsu, Li-Chung
    Chen, Hung-Ming
    [J]. ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 451 - +
  • [7] Low power Boundary Scan design
    Plíva, Z
    Novák, O
    [J]. BEC 2002: Proceedings of the 8th Biennial Baltic Electronic Conference, 2002, : 265 - 268
  • [8] Efficient scan chain design for power minimization during scan testing under routing constraint
    Bonhomme, Y
    Girard, P
    Guiller, L
    Landrault, C
    Pravossoudovitch, S
    [J]. INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS, 2003, : 488 - 493
  • [9] A scan matrix design for low power scan-based test
    Lin, SP
    Lee, CL
    Chen, JE
    [J]. 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 224 - 229
  • [10] An Improved Scan Design for Minimization of Test Power under Routing Constraint
    Cui, Aijiao
    Yu, Tingting
    Qu, Gang
    Li, Mengyang
    [J]. 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 629 - 632