On-chip high-Q inductor using wafer-level chip-scale package technology

被引：3

作者：

Yang, Hsueh-An ^{[1
]}

Wang, Chen-Chao ^{[1
]}

Zheng, Po-Jen ^{[1
]}

Wang, Wei-Chung ^{[1
]}

机构：

[1] Adv Semicond Engn Inc, Kaohsiung 811, Taiwan

来源：

2007 INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | 2007年

关键词：

high Q inductor; above IC process; and post-IC process;

D O I：

10.1109/IMPACT.2007.4433594

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper characterizes of spiral inductor on silicon wafer using post-IC process. There are two critical factors to affect Quality factor of on-chip spiral inductor; one is a resistance of inductor, the other is substrate loss induced by eddy current. This paper demonstrated 10 mu m thick Cu film of inductor structure, to reduce the inductor resistance, and 10 mu m thick BCB dielectric material, which is a low-k material, separates inductor structure and silicon wafer to reduce the substrate loss. The Quality factor is over 45 at 2.4 GHz with inductance of 0.5 nH. In application, this technology can provide fully CMOS compatible and low temperature process.

引用

页码：173 / 176

页数：4

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