Design and implementation of unified hardware for 128-bit block ciphers ARIA and AES

被引：6

作者：

Koo, Bonseok ^{[1
]}

Ryu, Gwonho ^{[1
]}

Chang, Taejoo ^{[1
]}

Lee, Sangjin ^{[2
]}

机构：

[1] Attached Inst ETRI, Network & Communicat Security Div, Taejon, South Korea

[2] Korea Univ, Ctr Informat Security Technol, Seoul 136701, South Korea

来源：

ETRI JOURNAL | 2007年 / 29卷 / 06期

关键词：

ARIA; AES; hardware architecture; resource sharing;

D O I：

10.4218/etrij.07.0207.0077

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

引用

页码：820 / 822

页数：3

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