Floating-point fused multiply-add architectures

被引：0
|
作者：
Quinnell, Eric [1 ]
Swartzlander, Earl E., Jr.
Lemonds, Carl
机构：
[1] Univ Texas Austin, AMD, Austin, TX 78712 USA
来源：
CONFERENCE RECORD OF THE FORTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1-5 | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Two new floating-point fused multiply-add architectures for the single instruction execution of (A x B) + C are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as 2 collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the Advanced Micro Devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.
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页码：331 / +
页数：2
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