Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA

被引：0

作者：

Bouchoux, S ^{[1
]}

Bourennane, EB ^{[1
]}

Paindavoine, M ^{[1
]}

机构：

[1] Univ Burgundy, LE21, F-21000 Dijon, France

来源：

ICIP: 2004 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1- 5 | 2004年

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance. logic cost. spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained based on four partial configurations of arithmetic decoder allows reducing significantly the number of logic cells (57%) in comparison with static implementation.

引用

页码：2841 / 2844

页数：4

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