Tinsel: a manythread overlay for FPGA clusters

被引：16

作者：

Naylor, Matthew ^{[1
]}

Moore, Simon W. ^{[1
]}

Thomas, David ^{[2
]}

机构：

[1] Univ Cambridge, Cambridge, England

[2] Imperial Coll London, London, England

来源：

2019 29TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) | 2019年

基金：

英国工程与自然科学研究理事会;

关键词：

D O I：

10.1109/FPL.2019.00066

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Commodity FPGA boards with advanced networking facilities have great potential in the construction of high-performance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, space-efficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.

引用

页码：375 / 383

页数：9

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