Modulo 2n ± 1 adder design using select-prefix blocks

被引：37
|
作者：
Efstathiou, C
Vergos, HT
Nikolos, D
机构：
[1] TEI Athens, Dept Informat, Athens 12210, Greece
[2] Comp Technol Inst, Patras 26221, Greece
来源：
IEEE TRANSACTIONS ON COMPUTERS | 2003年 / 52卷 / 11期
关键词：
modulo 2n +/- 1 adders; select-prefix adders; computer arithmetic; VLSI architectures;
D O I：
10.1109/TC.2003.1244938
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present new design methods for modulo 21, I adders. We use the same select-prefix addition block for both modulo 2(n) - 1 and diminished-one modulo 2(n) + 1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.
引用
收藏
页码：1399 / 1406
页数：8
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