A 62-6601GHz phase-locked loop in 0.13um CMOS technology

被引：1

作者：

Tsai, Kun-Hung ^{[1
]}

Liu, Shen-Iuan ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10617, Taiwan

来源：

2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | 2008年

关键词：

phase-locked loop; frequency dividers; clock generator; CMOS;

D O I：

10.1109/VDAT.2008.4542425

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 62-66.1GHz phase-locked loop (PLL) in 0.13um CMOS process. By employing a modified wide-range injection-locked frequency divider, the proposed PLL demonstrates the output frequency from 62 to 66.1GHz which allowing wideband application in unlicensed 60GHz radio. As the PLL operates at 66.09GHz, the measured phase noise at 1MHz offset is -74.5dBc/Hz. The proposed circuit consumes a power of 89mW from a 1.5V supply voltage.

引用

页码：113 / +

页数：2

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