The Design and Simulation of Signal Integrity for High-Speed Backplane based on VPX

被引：0
|
作者：
Meng Hua [1 ]
Yin Liang [1 ]
Tan Anju [1 ]
Wen Zhaojin [1 ]
机构：
[1] China Acad Engn Phys, Inst Elect Engn, Mianyang 621900, Si Chuan, Peoples R China
来源：
PROCEEDINGS OF THE 2015 10TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS | 2015年
关键词：
vpx; signal integrity; mixed-mode S-parameters; Back drill; differential Via;
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
The problems confronted in the design of highspeed backplane are analyzed from the aspect of signal integrity. Principles of VPX backplane and topology structure are introduced with specific analysis and design schemes provided from the aspect of stack design, place and route design, Via design etc. Simulation analysis is made in the frequency domain on the signal integrity of the differential transmission line in the VPX high-speed backplane with theory of mixed-mode S-parameters.
引用
收藏
页码：1661 / 1664
页数：4
相关论文
共 50 条
  • [31] Companies form high-speed backplane initiative
    不详
    CONNECTOR SPECIFIER, 2002, 18 (09) : COVER1 - +
  • [32] Enhancement of signal integrity and power integrity with embedded capacitors in high-speed packages
    Srinivasan, K.
    Muthana, P.
    Mandrekar, R.
    Engin, E.
    Choi, J.
    Swaminathan, M.
    ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 284 - +
  • [33] Power and Signal Integrity co-simulation via compressed macromodels of high-speed transceivers
    Signorini, G.
    Siviero, C.
    Grivet-Talocia, S.
    Stievano, I. S.
    2015 IEEE 19TH WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI), 2015,
  • [34] Design of high speed backplane bus based on GTL technique
    An, Q.
    Zhang, Q.M.
    Liu, S.B.
    Chen, J.Q.
    Wang, Y.F.
    Hedianzixue Yu Tance Jishu/Nuclear Electronics and Detection Technology, 2001, 21 (01):
  • [35] Signal integrity optimization of high-speed VLSI packages and interconnects
    Zhang, QJ
    Wang, F
    Nakhla, MS
    Bandler, JW
    Biernacki, RM
    48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 1073 - 1076
  • [36] Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
    Mehrdad Nourani
    Amir Attarha
    Journal of Electronic Testing, 2002, 18 : 539 - 554
  • [37] Sparsity Constrained Regression For High-Speed Signal Integrity Modeling
    Zhuo, Jiacheng
    He, Jiayi
    Kiguradze, Zurab
    Mutnury, Bhyrav
    Drewniak, James
    2019 ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS (EDAPS 2019), 2019,
  • [38] Signal integrity and EMC in high-speed electronic package integration
    Li, E. P.
    2007 ASIA-PACIFIC CONFERENCE ON APPLIED ELECTROMAGNETICS, PROCEEDINGS, 2007, : 7 - 10
  • [39] Via and reference discontinuity impact on high-speed signal integrity
    Kim, J
    Kim, J
    Rotaru, MD
    Chong, KC
    Iyer, MK
    2004 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SYMPOSIUM RECORD 1-3, 2004, : 583 - 587
  • [40] Signal integrity: Fault modeling and testing in high-speed SoCs
    Nourani, M
    Attarha, A
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2002, 18 (4-5): : 539 - 554
12345