A multilevel cache memory architecture for nanoelectronics

被引：0
|
作者：
Crawley, D [1 ]
机构：
[1] Univ London Univ Coll, Dept Phys & Astron, Image Proc Grp, London WC1E 6BT, England
来源：
NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/GLSV.1999.757453
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present a new multilevel cache memory architecture which uses only near-neighbour connections, thus eliminating long tracks and rendering the system suitable for nanoelectronic implementation. Operation of the memory is such that the most-recently accessed data is kept closest to the read-write port.
引用
收藏
页码：346 / 347
页数：2
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