QoS Policies and Architecture for Cache/Memory in CMP Platforms

被引:3
|
作者
Iyer, Ravi [1 ]
Zhao, Li [1 ]
Guo, Fei [1 ]
Illikkal, Ramesh [1 ]
Makineni, Srihari [1 ]
Newell, Don [1 ]
Solihin, Yan [1 ]
Hsu, Lisa [1 ]
Reinhardt, Steve [1 ]
机构
[1] Intel Corp, Santa Clara, CA 95051 USA
关键词
Quality of Service; CMP; Cache/Memory; Performance; Service Level Agreements; Resource Sharing Principles;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As we enter the era of CMP platforms with multiple threads/cores on the die, the diversity of the simultaneous workloads running on them is expected to increase. The rapid deployment of virtualization as a means to consolidate workloads on to a single platform is a prime example of this trend. In such scenarios, the quality of service (QoS) that each individual workload gets from the platform can widely vary depending on the behavior of the simultaneously running workloads. While the number of cores assigned to each workload can be controlled, there is no hardware or software support in today's platforms to control allocation of platform resources such as cache space and memory bandwidth to individual workloads. In this paper, we propose a QoS-enabled memory architecture for CMP platforms that addresses this problem. The QoS-enabled memory architecture enables more cache resources (i.e. space) and memory resources (i.e. bandwidth) for high priority applications based on guidance from the operating environment. The architecture also allows dynamic resource reassignment during run-time to further optimize the performance of the high priority application with minimal degradation to low priority. To achieve these goals, we will describe the hardware/software support required in the platform as well as the operating environment (O/S and virtual machine monitor). Our evaluation framework consists of detailed platform simulation models and a QoS-enabled version of Linux. Based on evaluation experiments, we show the effectiveness of a QoS-enabled architecture and summarize key findings/trade-offs.
引用
收藏
页码:25 / +
页数:3
相关论文
共 50 条
  • [1] Rate-Based QoS Techniques for Cache/Memory in CMP Platforms
    Herdrich, Andrew
    Illikkal, Ramesh
    Iyer, Ravi
    Newell, Don
    Chadha, Vineet
    Moses, Jaideep
    [J]. ICS'09: PROCEEDINGS OF THE 2009 ACM SIGARCH INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, 2009, : 479 - 488
  • [2] CMP cache architecture and the OpenMP performance
    Tao, Jie
    Hoang, Kim D.
    Karl, Wolfgang
    [J]. PRACTICAL PROGRAMMING MODEL FOR THE MULTI-CORE ERA, PROCEEDINGS, 2008, 4935 : 77 - +
  • [3] High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies
    Lin, Ing-Chao
    Chiou, Jeng-Nian
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (10) : 2149 - 2161
  • [4] Exploring DRAM Cache Architectures for CMP Server Platforms
    Zhao, Li
    Iyer, Ravi
    Illikkal, Ramesh
    Newell, Don
    [J]. 2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 55 - 62
  • [5] A cache coherence protocol for distributed memory platforms
    Sumoza, Rodolfo
    Castro, Jose Aguilar
    [J]. COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 2010, 25 (05): : 343 - 353
  • [6] An architecture for automated replacement of QoS policies
    Granville, LZ
    de Sá Coelho, GAF
    Almeida, MJB
    Tarouco, LMR
    [J]. ISCC 2002: SEVENTH INTERNATIONAL SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS, PROCEEDINGS, 2002, : 796 - 801
  • [7] A cache coherence protocol for distributed memory platforms
    Sumoza, Rodolfo
    Aguilar Castro, Jose
    [J]. COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 2011, 26 (01): : 13 - 23
  • [8] Co-scheduling HPC workloads on cache-partitioned CMP platforms
    Aupy, Guillaume
    Benoit, Anne
    Goglin, Brice
    Pottier, Loic
    Robert, Yves
    [J]. 2018 IEEE INTERNATIONAL CONFERENCE ON CLUSTER COMPUTING (CLUSTER), 2018, : 348 - 358
  • [9] Co-scheduling HPC workloads on cache-partitioned CMP platforms
    Aupy, Guillaume
    Benoit, Anne
    Goglin, Brice
    Pottier, Loic
    Robert, Yves
    [J]. INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS, 2019, 33 (06): : 1221 - 1239
  • [10] A multilevel cache memory architecture for nanoelectronics
    Crawley, D
    [J]. NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 346 - 347