High-performance twin silicon nanowire MOSFET (TSNWFET) on bulk Si wafer

被引：42
|
作者：
Suk, Sung Dae [1 ]
Yeo, Kyoung Hwan [1 ]
Cho, Keun Hwi [1 ]
Li, Ming [1 ]
Yeoh, Yuri Young [1 ]
Lee, Sung-Young [1 ]
Kim, Sung Min [1 ]
Yoon, Eun Jung [1 ]
Kim, Min Sang [1 ]
Oh, Chang Woo [1 ]
Kim, Sung Hwan [1 ]
Kim, Dong-Won [1 ]
Park, Donggun [1 ]
机构：
[1] Samsung Elect Co, Semicond Res & Dev Ctr, Dynam Random Access Memory Technol Dev Team, Kyoungi, South Korea
来源：
IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2008年 / 7卷 / 02期
关键词：
bulk MOSFET; gate all around (GAA); high performance; MOSFET; nanowire; TSNWFET; twin silicon nanowire; 5; nm;
D O I：
10.1109/TNANO.2008.917843
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/mu m for n-channel and 1.30 mA/mu m for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.
引用
收藏
页码：181 / 184
页数：4
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