High performance 5nm radius twin silicon nanowire MOSFET(TSNWFET) : Fabrication on bulk Si wafer, characteristics, and reliability

被引：0

作者：

Suk, SD ^{[1
]}

Lee, SY ^{[1
]}

Kim, SM ^{[1
]}

Yoon, EJ ^{[1
]}

Kim, MS ^{[1
]}

Li, M ^{[1
]}

Oh, CW ^{[1
]}

Yeo, KH ^{[1
]}

Kim, SH ^{[1
]}

Shin, DS ^{[1
]}

Lee, KH ^{[1
]}

Park, HS ^{[1
]}

Han, JN ^{[1
]}

Park, CJ ^{[1
]}

Park, JB ^{[1
]}

Kim, DW ^{[1
]}

Park, D ^{[1
]}

Ryu, B ^{[1
]}

机构：

[1] Samsung Elect Co, Device Res Team, Yongin 449711, Gyeonggi Do, South Korea

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

For the first time, we have successfully fabricated gate-all-around Twin Silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mu m, 1.11 mA/mu M for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, similar to 70 mV/dec. of substhreshold swing(SS), and similar to 20 mVN of Drain Induced Barrier Lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs.

引用

页码：735 / 738

页数：4

共 12 条

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