A 200 MHz 4.8 mW 3 V fully differential CMOS sample-and-hold circuit with low hold pedestal

A new technique for realizing a high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The design consideration of the building blocks is described in detailed. A prototype circuit in a 0.5-mu m CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 200 MHz of sampling frequency with less than -56.5 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8V(pp). In these conditions, a differential hold pedestal of less than 0.8 mV, 0.6 ns acquisition time at 0.8 V step input, and 0.8 V(pp) full-scale differential input range are achieved. The circuit dissipates 4.8 mW with a +/- 1.5 V power supply.