Development of SiGe Indentation Process Control for Gate-All-Around FET Technology Enablement

被引:9
|
作者
Schmidt, Daniel [1 ]
Cepler, Aron [2 ]
Durfee, Curtis [1 ]
Pancharatnam, Shanti [1 ]
Frougier, Julien [1 ]
Breton, Mary [1 ]
Greene, Andrew [1 ]
Klare, Mark [2 ]
Koret, Roy [3 ]
Turovets, Igor [3 ]
机构
[1] IBM Res, Albany, NY 12203 USA
[2] Nova Inc, Fremont, CA 94538 USA
[3] Nova Ltd, IL-7610201 Rehovot, Israel
关键词
Radar measurements; Silicon germanium; Optical interferometry; Spaceborne radar; Logic gates; Monitoring; Optical scattering; Gate-all-around FET; machine learning; nanosheet; scatterometry; x-ray fluorescence; interferometry;
D O I
10.1109/TSM.2022.3168585
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Methodologies for characterization of the lateral indentation of silicon-germanium (SiGe) nanosheets using different non-destructive and in-line compatible metrology techniques are presented and discussed. Gate-all-around nanosheet device structures with a total of three sacrificial SiGe sheets were fabricated and different etch process conditions used to induce indent depth variations. Scatterometry with spectral interferometry and x-ray fluorescence in conjunction with advanced interpretation and machine learning algorithms were used to quantify the SiGe indentation. Solutions for two approaches, average indent (represented by a single parameter) as well as sheet-specific indent, are presented. Both scatterometry with spectral interferometry as well as x-ray fluorescence measurements are suitable techniques to quantify the average indent through a single parameter. Furthermore, machine learning algorithms enable a fast solution path by combining x-ray fluorescence difference data with scatterometry spectra, therefore avoiding the need for a full optical model solution. A similar machine learning model approach can be employed for sheet-specific indent monitoring; however, reference data from cross-section transmission electron microscopy image analyses are required for training. It was found that scatterometry with spectral interferometry spectra and a traditional optical model in combination with advanced algorithms can achieve a very good match to sheet-specific reference data.
引用
收藏
页码:412 / 417
页数:6
相关论文
共 50 条
  • [31] Formation Mechanism of a Rounded SiGe-Etch-Front in an Isotropic Dry SiGe Etch Process for Gate-All-Around (GAA)-FETs
    Zhao, Yu
    Iwase, Taku
    Satake, Makoto
    Hamamura, Hirotaka
    [J]. 2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM), 2021,
  • [32] Process Technology Innovation for Performance Improvements in the Era of Horizontal Gate-All-Around (hGAA) Devices
    Breil, Nicolas
    [J]. 2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
  • [33] Impact of image force effect on gate-all-around Schottky barrier tunnel FET
    20162302454409
    [J]. (1) Faculty of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku-ku, Tokyo; 169-8555, Japan; (2) Graduate School of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki; 305-8573, Japan, 1600, (Institute of Electrical and Electronics Engineers Inc., United States):
  • [34] Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric
    Jung, Hakkee
    [J]. INTERNATIONAL JOURNAL OF ENGINEERING AND TECHNOLOGY INNOVATION, 2024, 14 (02) : 189 - 200
  • [35] C-V Characteristics in Undoped Gate-All-Around Nanowire FET Array
    Baek, Rock-Hyun
    Baek, Chang-Ki
    Lee, Sang-Hyun
    Suk, Sung Dae
    Li, Ming
    Yeoh, Yun Young
    Yeo, Kyoung Hwan
    Kim, Dong-Won
    Lee, Jeong-Soo
    Kim, Dae M.
    Jeong, Yoon-Ha
    [J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32 (02) : 116 - 118
  • [36] Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity
    Dasgupta, Avirup
    Hu, Chenming
    [J]. IEEE ELECTRON DEVICE LETTERS, 2020, 41 (12) : 1750 - 1753
  • [37] Impact of Image Force Effect on Gate-All-Around Schottky Barrier Tunnel FET
    Hashimoto, Shuichiro
    Kosugiyama, Hiroki
    Takei, Kohei
    Sun, Jing
    Kawamura, Yuji
    Shikahama, Yasuhiro
    Ohmori, Kenji
    Watanabe, Takanobu
    [J]. 2014 IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC), 2014,
  • [38] Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET
    Vishnoi, Rajat
    Kumar, M. Jagadesh
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (07) : 2599 - 2603
  • [39] Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET
    Kim, Soohyun
    Kim, Jungchun
    Jang, Doyoung
    Ritzenthaler, Romain
    Parvais, Bertrand
    Mitard, Jerome
    Mertens, Hans
    Chiarella, Thomas
    Horiguchi, Naoto
    Lee, Jae Woo
    [J]. APPLIED SCIENCES-BASEL, 2020, 10 (08):
  • [40] Impact of channel and spacer engineering on DC and RF performance of Gate-all-around FET
    Zhou, Zhen
    Sun, Ya-Bin
    Li, Xiao-Jin
    Shi, Yan-Ling
    Chen, Shou-Mian
    Hu, Shao-Jian
    Guo, Ao
    [J]. 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 15 - 17