共 27 条
- [21] A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory [J]. 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 913 - 916
- [25] A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET [J]. IEEE SOLID-STATE CIRCUITS LETTERS, 2020, 3 : 110 - 113
- [26] Novel 20nm hybrid SOI/bulk CMOS technology with 0.183 μm2 6T-SRAM cell by immersion lithography [J]. 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2005, : 16 - 17
- [27] A 28-GHz transceiver front-end with T/R switching achieving 11.2-dBm OP1dB, 33.8% PAEmax and 4-dB NF in 22-nm FD-SOI for 5G communication [J]. 2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2018,