Evaluation of process parameters for flip chip stencil printing

被引:4
|
作者
Nguty, TA [1 ]
Riedlin, MHA [1 ]
Ekere, NN [1 ]
机构
[1] Univ Salford, Dept Aeronaut Mech & Mfg Engn, Elect Manufacture & Assembly Grp, Salford M5 4WT, Lancs, England
关键词
D O I
10.1109/IEMT.1998.731077
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
As industry moves towards successful implementation of volume production of flip chip assembly, there is a lot of interest in achieving solder paste printing at the flip chip geometry. The advantages of this process are low cost and high throughput. However to meet this challenge there is a key need to evaluate the stencil printing process parameters. These process parameters can be divided into four groups: printer parameters, stencil parameters, environmental parameters, and solder paste parameters. The process parameters evaluated in this paper are the stencil and solder paste parameters. A variety of different stencils with a range of shapes, sizes and pitches were investigated. These dimensions determines the type of solder paste that can be printed. One approach currently adopted by the industry is to reduce the solder alloy particle size to facilitate paste flow through the very small stencil apertures. However, reducing the particle size in this way has been shown to radically affect the paste rheology and consequently the printing behaviour. In this paper we address the need for characterising new paste formulations, and present a procedure for evaluating solder pastes now being developed for flip chip application using the stencil printing process. Rheology is one means of characterising solder pastes. Rheological measurements are needed to correlate the behaviour of solder pastes to their performance in the stencil printing process. Fundamental procedures used in the industry for characterisation in shear conditions include rheograms (flow curves), thixotropic index and single point viscosity measurements. In particular, we show how viscosity changes can be quantified. Typical viscosity measurements were carried out on a controlled stress-strain Reologica StressTech rheometer with a parallel plate geometry. We also report on the characterisation of the creep/recovery properties of solder paste and how it can be correlated to slump. To correlate the measured solder rheological properties to the stencil printing behaviour, several printing trials were carried out. These trials can help in defining the process window for any given flip chip application, in terms of the limiting pitch size, pad size and the minimum gap between pads.
引用
收藏
页码:206 / 216
页数:5
相关论文
共 50 条
  • [1] Stencil printing process development for flip chip interconnect
    Li, L
    Thompson, P
    [J]. IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2000, 23 (03): : 165 - 170
  • [2] Optimising process parameters for flip chip stencil printing using Taguchi's method
    Rajkumar, D
    Nguty, T
    Ekere, NN
    [J]. TWENTY SIXTH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, PROCEEDINGS, 2000, : 382 - 388
  • [3] Stencil printing process development for low cost flip chip interconnect
    Li, L
    Wiegele, S
    Thompson, P
    Lee, R
    [J]. 48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 421 - 426
  • [4] Stencil printing technology for 100μm flip chip bumping
    Manessis, D
    Patzelt, R
    Ostmann, A
    Aschenbrenner, R
    Reichl, H
    [J]. 2003 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 2003, 5288 : 241 - 246
  • [5] Study of Stencil Printing Technology for Fine Pitch Flip Chip Bumping
    Yang, Jin
    Cai, Jian
    Wang, Shuidi
    Jia, Songliang
    [J]. 2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009), 2009, : 820 - 825
  • [6] Investigation of Wall-slip Effect on Paste Release Characteristic in Flip chip Stencil Printing Process
    Durairaj, R.
    Mallik, S.
    Seman, A.
    Marks, A.
    Ekere, N. N.
    [J]. EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 1328 - +
  • [7] Optimization of stencil printing wafer bumping for fine pitch flip chip applications
    Gong, JF
    Yau, EWC
    Chan, PCH
    Lee, RSW
    Yuen, MMF
    [J]. 53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 1724 - 1730
  • [8] Optimization of electroplating, stencil printing, ball placement solder-bumping flip-chip process technologies
    Xiao, GW
    Gong, JF
    Yau, EWC
    Chan, PCH
    Lee, RSW
    Yuen, MMF
    [J]. 53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 1850 - 1855
  • [9] Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process
    Kay, Robert W.
    Stoyanov, Stephen
    Glinski, Greg P.
    Bailey, Chris
    Desmulliez, Marc P. Y.
    [J]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2007, 30 (01): : 129 - 136
  • [10] Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping
    Manessis, D
    Patzelt, R
    Ostmann, A
    Aschenbrenner, R
    Reichl, H
    [J]. MICROELECTRONICS RELIABILITY, 2004, 44 (05) : 797 - 803