Multigate Ferroelectric Transistor Design Toward 3-nm Technology Node

被引：12

作者：

Choe, Gihun ^{[1
]}

Yu, Shimeng ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2021年 / 68卷 / 11期

关键词：

Iron; Logic gates; Transistors; FinFETs; FeFETs; Nanostructures; Semiconductor process modeling; Ferroelectric field-effect transistor (FeFET); ferroelectrics (FEs); FinFET; nanosheets; nonvolatile memory; FUTURE;

D O I：

10.1109/TED.2021.3108477

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An advanced gate-stack design of ferroelectric (FE) transistors has been proposed and investigated for logic compatible program/erase voltage, better scalability, and suppressed depolarization field. The ferroelectric-metal (FeM) FinFET (FeM-FinFET) and stacked nanosheets transistor (FeM-Nanosheet), which have an FE layer on top of the transistor's gate, could adjust the area ratio (AR) between the FE capacitor (A(FE)) and the MOS capacitor (A(MOS)) (AR = A(FE)/A(MOS)) using the floating gate between them, thereby enhancing the electric field on the FE layer. In particular, the proposed FeM-Nanosheet could have the flexibility to lower the operating voltage and depolarization field by increasing the number of nanosheets to reduce the AR.

引用

页码：5908 / 5911

页数：4

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