Breaking the 2n-bit carry propagation barrier in residue to binary conversion for the [2n-1, 2n, 2n+1] modula set

被引：32
|
作者：
Bhardwaj, M [1 ]
Premkumar, AB
Srikanthan, T
机构：
[1] Siemens Components, Microelect Design Ctr, Singapore 349249, Singapore
[2] Nanyang Technol Univ, Sch Appl Sci, Singapore 639798, Singapore
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS | 1998年 / 45卷 / 09期
关键词：
modular arithmetic; residue numbers; reverse converters;
D O I：
10.1109/81.721268
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents a high speed realization of a residue to binary converter for the {2(n-1),2(n),2(n) + 1} moduli set, which improves upon the best known implementation by almost twice in terms of overall conversion delay. This significant speedup is achieved by using just three extra two input logic gates. Interestingly, by exploiting certain symmetry in operands, we also reduce the hardware requirement of the best known implementation by n - 1 full adders. Finally, the proposed converter eliminates the redundant representation of zero using no extra logic.
引用
收藏
页码：998 / 1002
页数：5
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