A Wideband 5 GHz Digital PLL Using a Low-Power Two-Step Time-to-Digital Converter

被引：0

作者：

Hamza, A. ^{[1
]}

Ibrahim, S. ^{[1
]}

El-Nozahi, M. ^{[1
]}

Dessouky, M. ^{[1
]}

机构：

[1] Ain Shams Univ, Fac Engn, Integrated Circuits Lab, Elect & Commun Engn Dept, Cairo, Egypt

来源：

2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS) | 2015年

关键词：

Digital phase-locked loop (DPLL); time-to-digital converter (TDC); delta-sigma digital-to-analog converter (Delta Sigma-DAC); digital controlled oscillator (DCO); NM CMOS; OSCILLATOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of a wideband, low-jitter 5 GHz digital phase-locked loop (DPLL) in 65 nm CMOS. The DPLL uses a high-resolution, low-power two-step time-to-digital converter (TDC) to achieve a wide loop bandwidth (BW) with low jitter. The DPLL is designed with a loop BW of 4 MHz using a 100 MHz reference and achieves a root mean square (RMS) jitter and a peak-to-peak (PP) jitter of 1.59 ps and 20.69 ps respectively at 5 GHz operation. The DPLL occupies an area of 0.026 mm(2) and consumes 4.5 mA from a 1.2 V supply.

引用

页码：328 / 331

页数：4

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