Field Programmable Gate Array design for an application specific signal processing algorithms

Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. This paper presents a new FPGA architecture suitable for the application specific signal processing algorithms and Wafer-Scale Integration (WSI) Technology. The architecture must be designed for versatility, flexibility, high speed, improved logic density, and defect tolerance. The proposed FPGA architecture consists of 2 dimensional array of programmable logic elements based on look-up table, interconnection resources, and input/output (I/O) blocks. The architectural style is similar to the one used in XILINX FPGA architecture. A key variation from the commonly used FPGA is the dual switching scheme employed in the proposed architecture: 1) Laser Vertical Links (LVLs) (Moreno, 1993) designed and developed at the Center for Microelectronics Research, University of South Florida, that due to its low interconnect resistance, offer a high speed connection between the logic elements and the routing network. 2) Soft switching scheme (Walker, 1990) to route signals from one channel to the other. see figure 1. The other benefit that can be result from such a type arrangement is the defect tolerance. After fabrication, a defective logic element can be isolated by merely cutting the LVL's and bypassing it using the soft switches. An implementation of the proposed architecture was performed and tested on a benchmark circuit by using the Segmented Channel Routing Algorithm (Brown, 1996) to determine the optimal logic elements an ay size and to explore the relationship between the routability of an FPGA and the flexibility of its routing structure. That is to calculate the optimal number of switches required to achieve good routability, flexibility, and high speed. The design methodology. the design tools, and results obtained by using a Segmented Channel Routing Algorithm to map on it a 16 bit Parallel Multiplier. The results of this study for the selected benchmark circuit are presented.