Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits

被引：25
|
作者：
Yeh, Chih-Ting [1 ,2 ]
Ker, Ming-Dou [1 ,3 ]
Liang, Yung-Chih [2 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan
[2] Ind Technol Res Inst, Informat & Commun Res Labs, Circuit Design Dept, Hsinchu 31040, Taiwan
[3] I Shou Univ, Dept Elect Engn, Kaohsiung 840, Taiwan
来源：
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2010年 / 10卷 / 02期
关键词：
Diode; electrostatic discharge (ESD); layout; radio-frequency (RF); LOW-CAPACITANCE; SCR;
D O I：
10.1109/TDMR.2010.2043433
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.
引用
收藏
页码：238 / 246
页数：9
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