A common underlying architecture approach to test systems design

被引:0
|
作者
Macfarlane, SA
机构
关键词
D O I
10.1109/AUTEST.1997.633685
中图分类号
V [航空、航天];
学科分类号
08 ; 0825 ;
摘要
One of the biggest test related topics of this decade has been the use of COTS hardware and software. This has been driven by the need to reduce development and maintenance costs, and to by and achieve a commonality between test systems. The systems integrator then has the task of taking many different industry and de-facto standards, and seamlessly building them into the final system. This paper deals with the development of a Common Underlying Architecture (CUA) which forms the 'glue' to interface between many different standards such as ATLAS [1] and VXIplug&play. This provides an open development and run-time system where the customer can choose from several different software languages and operating systems, whilst maintaining a common operator interface, a degree of resilience to obsolescence and the capability to extend the use of the Test System. The concept and definition of a CUA is currently the subject of on-going studies within the UK MoD. Various packaging and mounting options are discussed which allow the system to be configured for the particular application from factory test through to rugged field deployable systems.
引用
收藏
页码:619 / 623
页数:5
相关论文
共 50 条
  • [31] Systems Engineering for Test: Implementation of Test Strategy & Architecture at Raytheon Missile Systems
    Manas, Joseph
    Guise, Louisa
    2013 7TH ANNUAL IEEE INTERNATIONAL SYSTEMS CONFERENCE (SYSCON 2013), 2013, : 305 - 311
  • [32] SIMPLICITY AND COMPLEXITY IN BACTERIAL FLAGELLAR FILAMENTS - A COMMON UNDERLYING DESIGN
    TRACHTENBERG, S
    ULTRAMICROSCOPY, 1990, 32 (02) : 196 - 197
  • [33] SOC test architecture design for efficient utilization of test bandwidth
    Goel, SK
    Marinissen, EJ
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2003, 8 (04) : 399 - 429
  • [34] Design Thinking Underlying Fully Integrated Systems
    Nagata, Mitsuhiko
    2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020), 2020,
  • [35] Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application
    Tran, X. -T.
    Thonnart, Y.
    Durupt, J.
    Beroulle, V.
    Robach, C.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2009, 3 (05): : 487 - 500
  • [36] An approach to design test oracle for aspect oriented software systems using soft computing approach
    Singhal, Abhishek
    Bansal, Abhay
    Kumar, Avadhesh
    INTERNATIONAL JOURNAL OF SYSTEM ASSURANCE ENGINEERING AND MANAGEMENT, 2016, 7 (01) : 1 - 5
  • [37] Architecture Design of Mobile Cloud and Prototype Test
    Cai, Zhiming
    Chen, Chongcheng
    Wang, Qinmin
    2013 8TH INTERNATIONAL ICST CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA (CHINACOM), 2013, : 615 - 621
  • [38] Architecture design of test range based on DoDAF
    Wang, Xue-Zheng
    Xu, Xue-Mei
    Xitong Gongcheng Lilun yu Shijian/System Engineering Theory and Practice, 2013, 33 (01): : 249 - 254
  • [39] Effective and efficient test architecture design for SOCs
    Goel, SK
    Marinissen, EJ
    INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 529 - 538
  • [40] Efficient design of system test: A layered architecture
    Baldini, A
    Benso, A
    Prinetto, P
    INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 930 - 939