Testing for SoCs with Advanced Static and Dynamic Power-Management Capabilities

Many multicore chips today employ advanced power management techniques. Multi-threshold CMOS (MTCMOS) is very effective for reducing standby leakage power. Dynamic voltage scaling and voltage islands which operate at multiple power-supply voltage levels, minimize dynamic power consumption. Effective defect screening for such chips requires advanced test techniques that target defects in the embedded cores and the power management structures. We describe recent advances in test generation and test scheduling techniques for SoCs that support power switches, voltage islands, and dynamic voltage scaling schemes.