Evaluation of novel carrier substrates for high reliability and integrated GaN devices in a 200 mm complementary metal-oxide semiconductor compatible process

被引:3
|
作者
Stoffels, S. [1 ]
Geens, K. [1 ]
Li, X. [1 ]
Wellekens, D. [1 ]
You, S. [1 ]
Zhao, M. [1 ]
Borga, M. [2 ]
Zanoni, E. [2 ]
Meneghesso, G. [2 ]
Meneghini, M. [2 ]
Posthuma, N. E. [1 ]
Van Hove, M. [1 ]
Decoutere, S. [1 ]
机构
[1] IMEC, PMST, Kapeldreef 75, Heverlee, Vlaams Brabant, Belgium
[2] Univ Padua, Dipartimento Ingn Informaz, Padua, Italy
关键词
D O I
10.1557/mrc.2018.192
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In this paper new materials and substrate approaches are discussed which have potential to provide (Al)GaN buffers with a better crystal quality, higher critical electrical field, or thickness and have the potential to offer co-integration of GaN switches at different reference potentials, while maintaining lower wafer bow and maintaining complementary metal-oxide semiconductor (CMOS) compatibility. Engineered silicon substrates, silicon on insulator (SOI) and coefficient of thermal expansion (CTE)-matched substrates have been investigated and benchmarked with respect to each other. SOI and CTE-matched offer benefits for scaling to higher voltage, while a trench isolation process combined with an oxide interlayer substrate allows co-integration of GaN components in a GaN-integrated circuit (IC).
引用
收藏
页码:1387 / 1394
页数:8
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