A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET

被引：5

作者：

Dermit, Davide ^{[1
]}

Shrivas, Mithlesh ^{[1
]}

Bunsen, Keigo ^{[2
]}

Benites, Jorge L. ^{[1
]}

Craninckx, Jan ^{[1
]}

Martens, Ewout ^{[1
]}

机构：

[1] IMEC, IMECBE SEA BEIOT, B-3001 Leuven, Belgium

[2] Sony Semicond Solut Corp, Atsugi, Kanagawa 2430021, Japan

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2020年 / 3卷

关键词：

5G; analog-to-digital converter (ADC); comparator-based asynchronous binary search (CABS); FinFET; ping-pong SAR (PP-SAR); SAR; split-source (SS) comparator; time-interleaved (TI);

D O I：

10.1109/LSSC.2020.3008264

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This letter introduces a novel SAR-based algorithm that speeds up the conversion by using two digital-to-analog converters that operate in a ping-pong fashion. It has been implemented in a 4x time-interleaved analog-to-digital converter in a 16-nm FinFET technology. Each channel uses the proposed ping-pong SAR (PP-SAR) algorithm in a coarse phase followed by a comparator-based asynchronous binary search (CABS) fine phase to realize 418 MHz/channel 10-bit conversion with 51-dB SNDR at Nyquist. The total power consumption is 7.9 mW corresponding to a Walden FoM of 16 fJ/conversion-step at Nyquist.

引用

页码：150 / 153

页数：4

共 3 条

[1] A 2.28mW 100 MS/s 10-bit ping-pong configuration SAR-assisted pipeline ADC
Mosalmani, A.
Qomi, M. Zahedi
Shoaei, O.
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2024, 118 (01) : 37 - 48
[2] A 2.28mW 100 MS/s 10-bit ping-pong configuration SAR-assisted pipeline ADC
A. Mosalmani
M. Zahedi Qomi
O. Shoaei
Analog Integrated Circuits and Signal Processing, 2024, 118 : 37 - 48
[3] A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization
Martens, Ewout
Hershberg, Benjamin
Craninckx, Jan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (04) : 1161 - 1171

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