Zippy - A coarse-grained reconfigurable array with support for hardware virtualization

被引：0

作者：

Plessl, C ^{[1
]}

Platzner, M ^{[1
]}

机构：

[1] Swiss Fed Inst Technol, Comp Engn & Networks Lab, Zurich, Switzerland

来源：

16TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURE AND PROCESSORS, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the nonvirtualized and the virtualized execution of an ADPCM decoder

引用

页码：213 / 218

页数：6

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