共 50 条
- [1] Architectural exploration of the ADRES coarse-grained reconfigurable array [J]. RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, 2007, 4419 : 1 - +
- [2] A New Array Fabric for Coarse-Grained Reconfigurable Architecture [J]. 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 584 - 591
- [3] Architecture enhancements for the ADRES coarse-grained reconfigurable array [J]. HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS, 2008, 4917 : 66 - +
- [4] Mapping Tasks to a Dynamically Reconfigurable Coarse-Grained Array [J]. 2014 IEEE 22ND ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2014), 2014, : 33 - 33
- [5] Zippy - A coarse-grained reconfigurable array with support for hardware virtualization [J]. 16TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURE AND PROCESSORS, PROCEEDINGS, 2005, : 213 - 218
- [6] Still image processing on coarse-grained reconfigurable array architectures [J]. 2007 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA, 2007, : 67 - +
- [7] A Novel LDPC Decoder Based on Coarse-Grained Reconfigurable Array [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON UBIQUITOUS WIRELESS BROADBAND (ICUWB2016), 2016,
- [8] Still Image Processing on Coarse-Grained Reconfigurable Array Architectures [J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2010, 60 (02): : 225 - 237
- [9] Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor [J]. INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2009, 5349 : 449 - +
- [10] Still Image Processing on Coarse-Grained Reconfigurable Array Architectures [J]. Journal of Signal Processing Systems, 2010, 60 : 225 - 237