A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32 nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5x and 1.06x higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4 V. Write static noise margin (WSNM) of the proposed design is 1.65x, 1.71x and 1.77x larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write "1" delay of the proposed cell is 0.108x and 0.81x as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40x lesser read power as compared to PPN10T cell at 0.4 V. Leakage power of the proposed cell is 0.35x of C6T cell at 0.4 V. Proposed 11T cell occupies 1.65x larger area as compared to that of conventional 6T.